In some applications, an integrated circuit chip that uses only n-channel MOS (NMOS) transistors must communicate with another integrated circuit chip that uses a complementary MOS (CMOS) transistor pair (a PMOS and an NMOS transistor) as its input. Such CMOS circuits typically require a significant input voltage swing, e.g., such as between 0.3 Vdd and 0.7 Vdd, where Vdd is a positive voltage coupled to the source of the PMOS transistor of the input CMOS pair and ground potential is coupled to the source of the NMOS transistor of the CMOS pair whose drain is coupled to the drain of the PMOS transistor, in order to provide a reliable recognizable input change.
One solution to this problem is to include a p-channel enhancement transistor on the same chip as the n-channel transistors and to use it in series with an n-channel transistor. This solution, in effect, results in the chip becoming a CMOS type integrated circuit, which adds considerable complexity to the fabrication process and is undesirable in some applications.
One prior art driver circuit often used as an output driver on an n-channel transistor chip is shown as driver circuit 10 in FIG. 1. Driver circuit 10 essentially comprises a first n-channel enhancement mode MOS transistor 12 and a second n-channel enhancement mode MOS transistor 14 with the source of transistor 12 being connected to the drain of transistor 14 and to an output terminal 18, with the drain of transistor 12 coupled to a positive voltage source Vdd, and with the source of transistor 14 coupled to ground potential. The gate of transistor 12 is coupled to an input terminal 13 and to an input of an inverter 16 which has an output that is connected to the gate of transistor 14 and to a terminal 15. The channels of NMOS transistors 12 and 14 are shown with two "+'s" in each to indicate that a conventional p-type implant was made into the channel of each to raise the threshold voltages and help prevent unwanted inversion of the channels. This implant is important to overcome the natural tendency of the surface of the channel of an NMOS transistor, formed in a typical lightly doped p-type substrate, otherwise to behave as n-type, in which case the transistor can act as a depletion mode transistor with appreciable surface current between the heavily doped source and drain of the transistor, even without any applied gate voltage. The implant is used to set the potential of the surface and thereby to insure that the transistor operate in the desired enhancement mode. Typically, the implant is used to increase the surface doping to about 1.times.10.sup.16 impurities/cm.sup.3 while the bulk of the p-type substrate (not shown) retains its original doping, typically about 1.times.10.sup.15 impurities/cm.sup.3. Inverter 16 is used to insure that opposite logic signals are applied to the gates of transistors 12 and 14.
With a "1" input signal (e.g., a voltage level at or near the voltage level of Vdd) applied to input terminal 13, transistor 12 is biased on (enabled) and transistor 14 is biased off (disabled). These conditions cause output terminal 18 to assume a voltage level of Vdd less the Vth (threshold of transistor 12). Typically, Vth of transistor 12 is about +0.7 volts (plus or minus 0.2 volts) with a zero back gate bias for the example mentioned where the impurity concentration of the p-type substrate (not shown in this figure) on which transistor 12 is fabricated is 1.times.10.sup.15 impurities/cm.sup.3 and the p-type implant into the channel region of transistor 12 result in increasing the impurity concentration in the channel region to about 1.times.10.sup.16 impurities/cm.sup.3. In some applications, including applications in which a CMOS inverter circuit is to be the load connected to output terminal 18, the output voltage representing a "1" is not high enough to reliably switch the load circuit. In such case, a buffer circuit or voltage multiplier circuit must be inserted between the driver circuit and the load for reliable operation.
The above described prior art two serially connected n-channel MOS transistor driver circuit can be modified to include bootstrapping circuitry so as to increase the gate potential of the first transistor.
This modified circuit can generate higher output "1" levels but requires additional components and complexity.
It is desirable to have a circuit driver essentially comprised of a serially connected pair of n-channel enhancement mode MOS transistors in which the output voltages are completely compatible with the input voltages needed reliably to control conventional CMOS circuitry.